The present invention relates to a successive-approximation analog-digital converter.
The use of analog-digital converters that use a successive approximation technique, that is in which an analog signal is converted into a digital signal at N bits in N clock cycles, is generally known in the technical field. The converter basically consists of a comparator, a digital-analog converter (DAC) and a digital control logic. The function of the digital control logic is to determine the value of each bit by a sequential mode based on the output of the comparator. The cycle of conversion starts by sampling the analog input signal that has to be converted; however if the input signal is slowly variable that is, basically a signal that has a variation less than the least significant bit (LSB) for the duration of a conversion, the sampling of the input signal can be avoided. Then the logic control circuit assumes that the most significant bit (MSB) is 1 and all the other bits 0. The digital signal is sent to the DAC which generates an analog signal, for example of 0.5 Vref, where Vref is a reference voltage, which is compared with the analog input signal already sampled. If the output of the comparator is high the digital control logic makes the MSB 1, otherwise if the output of the comparator is low the digital control logic makes the MSB 0. This completes the first step in the approximation sequence. At this point, the value of the most significant bit is known.
The approximation sequence continues another time sending a digital signal to the DAC, with the most significant bit at its indicated value, the second bit placed at 1 and all the other bits which have a value 0. The comparison between the input signal sampled and the output of the DAC is again made; if the output of the comparator is high, the second bit is placed at 1, otherwise the second bit is placed at 0. The process continues in this manner until all the bits of the digital signal have been determined by the successive approximation process and therefore the number of cycles required for the conversion of an analog signal in a word of N bits is N.
In the case in which it is necessary to convert slowly variable signals, that is such that they do not significantly vary between one conversion and the next one (basically a signal with a variation that is less than one LSB (the least significant bit) for the duration of one conversion), given that said signals can be affected by disturbances (for example, noise) which cause undesired rapid variations in given periods of time, the digital output signal from an analog-digital converter like the above mentioned one will present anomalies. In particular, if the slowly variable analog signals that present oscillation in correspondence with the transition threshold between the value of the digital signal and the value of the continuous signal are considered, said oscillations may cause anomalies in the systems that have to be controlled by the converted digital signal.
In view of the state of the technique described, the object of the present invention is to present a successive-approximation analog-digital converter which overcomes the above mentioned drawback.
According to the present invention, such object is reached by means of a successive-approximation analog-digital converter comprising a logic control circuit timed by an external clock signal, said control circuit being adapted to produce a digital signal formed of N bits through a second analog-digital conversion in N clock cycles; a digital-analog converter that converts said digital signal sent by said logic circuit to an analog signal; a comparator which compares said analog signal with an analog signal at the input of said analog-digital converter, characterized in that said logic control circuit comprises a register which contains a previous digital signal formed of N bits and obtained from a previous analog digital conversion and said analog-digital converter comprise a device which enables the increase of said analog signal in output from the digital-analog converter and in input to said comparator by a preset value when the bit of said previous digital signal which corresponds in position to the bit of said digital signal which has to be decided in a clock cycle is a zero.
Moreover, according to the present invention, a method for the conversion of an analog signal to a digital signal as described herein, can be made.
Thanks to the present invention it is possible to make a successive-approximation analog-digital converter which, by the addition of a hysteresis at the DAC output, permits the elimination of the anomalies presented by known successive-approximation analog-digital converters in case of conversion of a slowly variable signal which presents oscillations at the transition threshold between the value of the digital signal and the value of the continuous signal.